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ITO Kazuhito

Faculty: Graduate School of Science and Engineering TEL:
Position: Vice President  Professor ■FAX:
Address: 255 Shimo-Okubo, Sakura-ku, Saitama City, Saitama 338-8570, JAPAN ■Mail Address:
■Web site:

Profile

Assigned Class

Faculty of Engineering
Vice President

Academic Societies

Academic Societies
IEEE

Academic Background

Degree
Ph.D. in Engineering , Tokyo Instutute of Technology , VLSI System Complier for Digital Signal Processing

Research Career

Research Career
2015 , Professor, Graduate School of Science and Engineering
2008 - 2015 , Associate professor, Graduate School of Science and Engineering

Research

Books, Articles, etc.

Articles
Reduction of LSI Maximum Power Consumption with Standard Cell Library of Stack Structured Cells
,IEICE Trans. Fundamentals,E105-A(3):487-496 2022
Yuki Imai, Shinichi Nishizawa, Kazuhito Ito

Register Minimization and its Application in Schedule Exploration for Area Minimization for Double Modular Redundancy LSI Design
,IEICE Trans. Fundamentals,E105-A(3):530-539 2022
Yuya Kitazawa, Kazuhito Ito

画像処理によるGUI 自動検証システムの構築
,自動車技術,76(3):104-110 2022
新井正敏, 伊藤和人

画像特徴点を使ったGUIシステムの自動実装検証の開発
,システム制御情報学会論文誌,34(1):23-25 2021
新井正敏, 伊藤和人

Energy Minimization of Double Modular Redundant Conditional Processing by Common Condition Dependency
,IEICE Transactions on Electronics,E103-C(4):181-185 2020
Kazuhito Ito

Analog circuit design methodology utilizing a structure of thin BOX FDSOI
,IEICE Electronics Express,16(5):20181136 2019
Kota Chubachi, Shinichi Nishizawa, Kazuhito Ito

Minimization of Energy Consumption of Double Modular Redundancy Design of Conditional Processing by Common Condition Dependency
,Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies:18 - 23 2019
Kazuhito Ito

Register Minimization in Double Modular Redundancy Design with Soft Error Correction by Replay
,Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies:192 - 197 2019
Yuya Kitazawa, Shinichi Nishizawa, Kazuhito Ito

1群4編2章回路解析の基礎
,知識ベース知識の森・電子情報通信学会:1-22 2019
伊藤和人(分担)

1群4編3章動的システムとしての回路
,知識ベース知識の森・電子情報通信学会:1-14 2019
伊藤和人(分担)

Minimization of Vote Operations for Soft Error Detection in DMR Design with Error Correction by Operation Re-Execution
,IEICE Trans. Fundamentals,E101-A(12):2271-2279 2018
Kazuhito Ito, Yuto Ishihara, Shinichi Nishizawa

Minimization of Equality Check for Soft Error Detection in DMR Design Implemented with Error Correction by Operation Re-execution
,Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies:112-117 2018
Yuto Ishihara, Shinichi Nishizawa, Kazuhito Ito

Low Complexity Reed-Solomon Decoder Design with Pipelined Recursive Euclidean Algorithm
,IEICE Transactions on Fundamentals,E99-A(12):2453-2462 2016
Kazuhito Ito

Hardware-Efficient Local Extrema Detection for Scale-Space Extrema Detection in SIFT Algorithm
,IEICE Transactions on Fundamentals,E99-A(12):2507-2510 2016
Kazuhito Ito, Hiroki Hayashi

Register-Bridge Architecture and its Application to Multiprocessor Systems
,Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies:10-15 2016
Takafumi Fujii, Shinichi Nishizawa, Kazuhito Ito

A Low Power and Hardware Efficient Syndrome Key Equation Solver Architecture and Its Folding with Pipelining
,IEICE Transactions on Fundamentals,E98-A(5):1058-1066 2015
Kazuhito ITO

Minimization of Register Area Cost for Soft-Error Correction in Low Energy DMR Design
,Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies:56-61 2015
Kazuhito Ito, Takumi Negishi

Energy Minimization of Full TMR Design with Optimized Selection of Temporal/Spatial TMR Mode and Supply Voltage
,IEICE Trans. Fundamentals,E97-A(12):2530-2539 2014
Kazuhito Ito

低消費電力シンドローム基本方程式求解アーキテクチャ
,電子情報通信学会論文誌,J96-A(9):691-694 2013
伊藤和人

高速ヴィタビ復号の先見ACS計算レイテンシ削減手法
,電子情報通信学会論文誌,J96-A(9):695-698 2013
伊藤和人, 白坂龍人, 大西秀児

A Parallel Simulated Annealing Algorithm with Look-Ahead Neighbor Solution Generation
,Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies:106-111 2013
Yusuke Ota, Kazuhito Ito

A Low Energy Full TMR Design Method with Optimized Selection of Time/Space TMR Mode and Supply Voltage
,Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies:334-339 2013
Kazuhito Ito, Yuki Hayashi

Hardware Efficient and Low Latency Implementations of Look-Ahead ACS Computation for Viterbi Decoders
,IEICE Transactions on Fundamentals,E96-A(12):2680-2688 2013
Kazuhito Ito, Ryoto Shirasaka

A Method to Reduce Energy Consumption of Conditional Operations with Execution Probabilities
,IPSJ Transactions on System LSI Design Methodology,6:60-70 2013
Kazuhito Ito, Kazuhiko Kameda

Valid Digit and Overflow Information to Reduce Energy Dissipation of Functional Units in General Purpose Processors
,IEICE Transactions on Electronics ,E96-C(4):463-472 2013
Kazuhito ITO, Takuya NUMATA

A Method of Power Supply Voltage Assignment and Scheduling of Operations to Reduce Energy Consumption of Error Detectable Computations
,Proceedings of the Workshop on Synthesis And System Integration of Mixed Information Technologies 2012:420-424 201203
Yuki Suda, Kazuhito Ito

A Trace-Back Method with Source States and its Application to Viterbi Decoders of Low Power and Short Latency
,Proceedings of the Workshop on Synthesis And System Integration of Mixed Information Technologies 2012:372-377 201203
Kazuhito Ito

A Trace-Back Method with Source States for Viterbi Decoding of Rate-1/n Convolutional Codes
,IEICE Transactions on Fundamentals,E95-A(4):767-775 2012
Kazuhito Ito
The Viterbi algorithm is widely used for decoding of the convolutional codes. The trace-back method is preferable to the register exchange method because of lower power consumption especially for convolutional codes with many states. A drawback of the conventional trace-back is that it generally requires long latency to obtain the decoded data. In this paper, a method of the trace-back with source states instead of decision bits is proposed which reduces the number of memory accesses. The dedicated memory is also presented which supports the proposed trace-back method. The reduced memory accesses result in smaller power consumption and a shorer decode latency than the conventional method.

A Processor Accelerator for Software Decoding of Reed-Solomon Codes
,IEICE Transactions on Fundamentals,E95-A(5):884-893 2012
Kazuhito ITO, Keisuke NASU

A Resource Binding Method to Reduce Data Communication Power Dissipation on LSI
情報処理学会,IPSJ Transactions on System LSI Design Methodology,3:257-267 201008
Hidekazu Seto, Kazuhito Ito

A Processor Accelerator for Software Decoding of BCH Codes
電子情報通信学会,IEICE Transactions on fundamentals of electronics, communications and computer sciences,E93-A(7):1329-1337 201007
Kazuhito Ito

Energy Dissipation Reduction of Arithmetic Operations with Valid Digits
,Proceedings of the Workshop on Synthesis And System Integration of Mixed Information Technologies 2009:35-40 2009
Kazuhito Ito, Yorito Nagasaka

FPGA を用いた並列 FFT の実現
埼玉大学地域オープンイノベーション,埼玉大学地域オープンイノベーションセンター紀要,1:67-72 2009
伊藤和人

Reducing Power Dissipation of Data Communictions on LSI with Scheduling Exploration
,IPSJ Transactions on System LSI Design Methodology,2:53-63 2009
Kazuhito Ito, Hidekazu Seto

A BCH Accelerator for Application Specific Processors
,Proceedings of the Workshop on Synthesis And System Integration of Mixed Information Technologies 2007:115-121 2007
Kazuhito Ito

スケジューリングとバス分割によるVLSI消費電力削減
埼玉大学総合研究機構,総合研究機構研究プロジェクト研究成果報告書,第5号(18年度):689-690 2007
伊藤和人

Schedule Exploration for Minimizing Energy Consumption by Data Communications
,Proceedings of the Workshop on synthesis And System Integration of Mixed Information Technologies 2006,-:308-313 2006
Kazuhito Ito

Rapid and Precise Instruction Set Evaluation for Application Specific Processor Design
,The Proceedings of IEEE International Symposium on Circuits and Systems,-:6210-6213 2005
Masayuki Masuda, Kazuhito Ito

自己ハザードによりステージ数を節約したCISCパイプラインプロセッサの自動生成
,第18回回路とシステム軽井沢ワークショップ論文集,-:569-574 2005
王佶, 山口達彦, 伊藤和人

Spatially Unequal Error Protection in Video Coding for Low SNR Channels
,Proc. IEEE International Midwest Symposium on Circuits and Systems,I:249 254 2004
Kazuhito Ito, Hiroshi Yamamoto

New Rate Control Method with Minimum Skipped Frames for Very Low Delay in H.263+ Codec
電子情報通信学会,IEICE Transactions on fundamentals of electronics, communications and computer sciences,E85-A(6):1396-1407 200206
伊藤和人

Systm-MSPA Design of H.263+ Video Encoder/Decoder LSI for Videotelephony Applications(Special Section on VLSI Design and CAD Algorithms)
電子情報通信学会,IEICE Transactions on fundamentals of electronics, communications and computer sciences,E84-A(11):2614-2622 200111
伊藤和人

An Overlapped Scheduling Method for an Iterative Processing Algorithm with Conditional Operations
電子情報通信学会,IEICE Transactions on fundamentals of electronics, communications and computer sciences,E81-A(3):429-438 199803
伊藤和人

Bits Truncation Adaptive Pyramid Algorithm for Motion Estimation of MPEG2 (Special Section on Digital Signal Processing)
電子情報通信学会,IEICE Transactions on fundamentals of electronics, communications and computer sciences,E80-A(8):1438-1445 199708
伊藤和人

Presentation
LSIの最大消費電力を削減するスタック構造スタンダードセルライブラリ
電子情報通信学会,電子情報通信学会技術報告VLD2019-101,119(443):43-48 202002
今井祐貴、西澤真一、伊藤和人

フリップフロップの記憶保持特性とIDDQテストを組み合わせたプロセスばらつき推定
電子情報通信学会,電子情報通信学会技術報告VLD2019-102,119(443):49-52 202002
西澤真一、伊藤和人

薄膜FDSOIトランジスタを用いた低電圧動作逆方向バイアス電圧生成回路
DAシンポジウム,DAシンポジウム2017論文集:75-78 201808
中鉢 洸太, 西澤 真一, 伊藤 和人

二重冗長化処理の誤り検出最少化スケジューリング手法
電子情報通信学会ソサイエティ大会:A-1-7 201709
石原裕人,西澤真一, 伊藤和人

二重冗長化処理におけるレジスタ面積コスト最小化
電子情報通信学会ソサイエティ大会:A-1-8 201709
伊藤和人

GPGPUによるFPGA向けテクノロジマッピングの高速化
電子情報通信学会総合大会,講演論文集:A-6-2 201603
杉山方健, 西澤真一, 伊藤和人

乗算器数を削減した低電力シンドローム基本方程式求解手法
電子情報通信学会2014年ソサイエティ大会,電子情報通信学会2014年ソサイエティ大会講演論文集:A-3-4 201409
伊藤和人

先見近傍解生成による焼きなまし法の並列化手法
電子情報通信学会,技術研究報告VLD2012-73,112(320):81-86 201211
太田悠介, 伊藤和人

A Method to Reduce Power Dissipation of Conditional Operations with Execution Probabilities and its Application to Dual Supply Voltage System
電子情報通信学会,電子情報通信学会技術報告,VLD2009-44:19-24 200912
Kazuhito Ito, Hyun-Joon Kim

A Resource Binding Method to Reduce Data Communication Power Dissipation on LSI
電子情報通信学会,電子情報通信学会技術報告,VLD2009-45:25-30 200912
Hidekazu Seto, Kazuhito Ito

LSIのデータ通信消費電力を削減するリソースバインディング手法
電子情報通信学会,電子情報通信学会技術報告(VLD2007-86):25-30 200711
世渡秀和、伊藤和人

埼玉大学FTTLの構築
学術情報処理研究集会,学術情報処理研究,11:124-128 200709
伊藤和人, 田邊俊治, 小川康一, 吉浦紀晃, 重原孝臣, 前川仁

動画像コーデックにおける主観的画質改善のための空間的不均一誤り保護
電子情報通信学会,電子情報通信学会技術報告(IE2006-279):23-28 200703
柴田太郎, 伊藤和人

Schedule Exploration for Minimizing Energy Consumption by Data Communications
,Proceedings of the Workshop on synthesis And System Integration of Mixed Information Technologies 2006:308-313 2006

フロアプランと高位合成を同時に行うLSI設計手法
電子情報通信学会,電子情報通信学会技術報告(CPSY2004-94):25-30 200503
大塚正臣, 伊藤和人

再構成可能加算を考慮したLSI高位設計手法
電子情報通信学会,電子情報通信学会技術報告(CPSY2004-95):31-36 200503
渡辺貴宏, 伊藤和人

Rapid and Precise Instruction Set Evaluation for Application Specific Processor Design
,The Proceedings of IEEE International Symposium on Circuits and Systems:6210-6213 2005

スケジューリング探索によるデータ通信消費電力削減
電子情報通信学会,電子情報通信学会技術報告(CPSY2005-81):25-30 2005
伊藤和人

自己ハザードによりステージ数を節約したCISCパイプラインプロセッサの自動生成
,第18回回路とシステム軽井沢ワークショップ論文集:569-574 2005

専用プロセッサ設計のためのレジスタ数を考慮した命令セット評価手法
電子情報通信学会,電子情報通信学会技術報告(CPSY2005-65):7-12 2005
増田雅由, 伊藤和人

専用プロセッサの命令セット評価の高速化手法
電子情報通信学会,電子情報通信学会技術報告(VLD2004-51):13-18 200412
増田雅由, 伊藤和人

Spatially Unequal Error Protection in Video Coding for Low SNR Channels
,Proc. IEEE International Midwest Symposium on Circuits and Systems:249-254 2004

自己ハザードによるCISCパイプラインプロセッサのメモリアクセスステージ低減手法
,電子情報通信学会技術報告(VLD2003-91):172-132 2003

An Optimal Scheduling Method for Parallel Processing System of Array Architecture
,Proc. 1997 Asia and South Pacific Design Automation Conference:447-454 1997

Bits Truncation Adaptive Pyramid Algorithm for Motion Estimation of MPEG2
,IEICE Trans. Fundamentals,E80-A(8):1438-1445 1997

High Speed Bit-Serial Parallel Processing on Array Architecture
,Proc. 1997 Asia and South Pacific Design Automation Conference:667-668 1997